
/////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 05/01/2013 
// Design Name: ALU
// Module Name: ALU
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: The 7-Segment LED Display module drives the 4 separate LED
// 7-Segment LED Display devices mounted on the FPGA Board.
//
// Dependencies:
// - my_clock
//
// Revision 0.01 - File Created
// Additional Comments:
// - I have provided the entire alphabet so that you can change this to display
//   other text as well.
/////////////////////////////////////////////////////////////////////////////////



module slowclock 
  /*************************************************************************
   * Input/Output Declarations and Parameters                              *
   *************************************************************************/
  (// Global Signals                  // -----------------------------------
   input  wire clk,                   // System Clock
   output wire clk_800Hz);            // 

   parameter MSB = 16;

  /***********************************************************
   * Signal Declaration                                      *
   ***********************************************************/   
   reg [MSB:0] count1 = 0;

  /***********************************************************
   * Combinational Logic                                     *
   ***********************************************************/
   assign clk_800Hz = count1[MSB];

  /***********************************************************
   * Synchronous Logic                                       *
   ***********************************************************/
   always@(posedge clk)
      count1 <= count1 + 1;
	  
  /***********************************************************
   * Module Instantiation                                    *
   ***********************************************************/	  
endmodule

module seg_display 
  /*************************************************************************
   * Input/Output Declarations and Parameters                              *
   *************************************************************************/
  (// Global Signals                  // -----------------------------------
   input wire         sys_clk,            // System Clock
   input wire         reset_b,        // Push Button for System Reset.
   // 7-Segment LED Interface         // -----------------------------------
   //input  wire [07:00]  read_data, 	  // 8bit input
	//input  wire          reg_read,     // Register Select Address is valid
   output  wire [01:00]  reg_addr,     // Register Select
   input  wire [03:00]  reg_data,     // 4-Bit register Value of currently
                                      // address register (valid it read is
                                      // active)
   // 7-Segment LED Display Interface // -----------------------------------
   output wire         dp_dis,        // Period Display
   output reg  [03:00] dis_control,   // Select which of the 4x7-Segment LED 
	                                  // Displays to activate.
   output reg  [06:00] led_dis);      // Select which of the 7 LED's in the 
	                                  // 7-Segment LED Display

   ///////////////////////////
   // 7-Segment LED Display //
   //       aaaaaaaa        //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //       ggggggggg       //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //       ddddddddd       //
   ///////////////////////////
   //                   6543210
   //                   gfedcba
	parameter _dash_ = 7'b0111111;
   parameter _0_ = 7'b1000000;
   parameter _1_ = 7'b1111001;
   parameter _2_ = 7'b0100100;
   parameter _3_ = 7'b0110000;
   parameter _4_ = 7'b0011001;
   parameter _5_ = 7'b0010010;
   parameter _6_ = 7'b0000010;
   parameter _7_ = 7'b1111000;
   parameter _8_ = 7'b0000000;
   parameter _9_ = 7'b0010000;
   parameter A   = 7'b00001000;
   parameter B     = 7'b0000011;
   parameter C     = 7'b1000110;
   parameter D     = 7'b0100001;
   parameter E     = 7'b0000110;
   parameter F     = 7'b0001110;
   parameter G     = 7'b0010000;
   parameter H     = 7'b0001011;
   parameter I     = 7'b1001111;
   parameter J     = 7'b1100001;
   parameter K     = 7'b0001001;
   parameter L     = 7'b1000111;
   parameter M     = 7'b1101010;
   parameter N     = 7'b0101011;
   parameter O     = 7'b1000000;
   parameter P     = 7'b0001100;
   parameter Q     = 7'b0011000;
   parameter R     = 7'b0101111;
   parameter S     = 7'b0010010;
   parameter T     = 7'b0000111;
   parameter U     = 7'b1000001;
   parameter V     = 7'b1100011;
   parameter W     = 7'b1010101;
   parameter X     = 7'b0001001;
   parameter Y     = 7'b0010001;
   parameter Z     = 7'b0100100;
   parameter empty = 7'b1111111;

  /***********************************************************
   * Signal Declaration                                      *
   ***********************************************************/
   wire        clk_800Hz;
   reg [01:00] count;

  /***********************************************************
   * Combinational Logic                                     *
   ***********************************************************/
   assign dp_dis = 1'b1; // Disable to dot.

  /***********************************************************
   * Synchronous Logic                                       *
   ***********************************************************/

	
	//Two busses one for 
	wire [3:0]dis_data;
	reg [6:0]converted_data;
	//split the input data into two busses. data[0] = LSB, data[1] = MSB
	
	
	integer i;
	
	
	//Combinational Logic. Converts the hexdecimal input from FIFO into a seven segment display digits.
	
	always @(*)
	begin
		if (~reset_b) begin
			converted_data = _dash_;
		end
		else begin 
			
				case (reg_data)
				4'h0:
					converted_data = _0_;
				4'h1:
					converted_data= _1_;
				4'h2:
					converted_data= _2_;
				4'h3:
					converted_data= _3_;
				4'h4:
					converted_data= _4_;
				4'h5:
					converted_data= _5_;
				4'h6:
					converted_data= _6_;
				4'h7:
					converted_data= _7_;
				4'h8:
					converted_data= _8_;
				4'h9:
					converted_data= _9_;
				4'hA:
					converted_data= A;
				4'hB:
					converted_data= B;
				4'hC:
					converted_data= C;
				4'hD:
					converted_data= D;
				4'hE:
					converted_data= E;
				4'hF:
					converted_data= F;				
				default:
					converted_data= empty;
				endcase
			
		end
	end
	assign reg_addr = count;
	/*active high reset!!!! We may need to change this to active low but it seems to work with this way so i'm not sure.*/
   always @(posedge clk_800Hz, negedge reset_b)
      if (~reset_b) begin
         count <= 2'd0;
			//dis_timer <= 1'b0;
			led_dis <= empty;
			dis_control <= 4'b1111;
      end
      else begin
			led_dis <= converted_data;
			// increase the count
         count  <= count + 1;
			
			// read another register every clock cycle, and display its value to the correct display
         case (count)
            0 : begin
				dis_control <= 4'b1110;
				
			end
            1 : begin
				dis_control <= 4'b1101;
				
			end
            2 : begin
				dis_control <= 4'b1011;
				
			end
            3 : begin
				dis_control <= 4'b0111;
				
			end
         endcase
      end

  /***********************************************************
   * Module Instantiation                                    *
   ***********************************************************/
   slowclock
      my_clock (
         .clk       (sys_clk),        // I      50MHz
         .clk_800Hz (clk_800Hz)); // I      800Hz

endmodule
